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holtek 32-bit microcontroller with arm ? cortex?-m3 core ht32f1251/51b/52/53 series datasheet revision: v1.10 date: ??? i? 1?? ?01? ???i? 1?? ?01?
rev. 1.10 ? of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? table of contents table of contents 1 general description ................................................................................................ 6 2 features ................................................................................................................... 7 co?e ....................................................................................................................................... 7 on-chi? memo?y .................................................................................................................... 7 f?ash memo?y cont?o??e? ....................................................................................................... 8 reset cont?o? unit ................................................................................................................. 8 c?ock cont?o? unit .................................................................................................................. 8 powe? management ............................................................................................................... 9 ?na?og to digita? conve?te? .................................................................................................... 9 analog operational amplifer/comparator ............................................................................. 9 i/o po?ts ............................................................................................................................... 10 pwm gene?ation and ca?tu? e time?s ................................................................................. 10 watchdog time ? ................................................................................................................... 11 rea? time c?ock ................................................................................................................... 11 inte?-integ?ated ci?cuit (i ? c) ................................................................................................. 1? se?ia? pe?i?he?a? inte?face (spi) .......................................................................................... 1? unive?sa? synch?onous ?synch?onous receive? t ?ansmitte? (us? rt) ............................... 1? debug su??o?t ..................................................................................................................... 1? package and o?e? ation tem?e?atu?e .................................................................................. 1? 3 overview ................................................................................................................ 14 device info?mation ............................................................................................................... 14 b?ock diag?am ..................................................................................................................... 15 memo?y ma? ........................................................................................................................ 16 c?ock st?uctu?e .................................................................................................................... 17 pin ?ssignment .................................................................................................................... 18 4 electrical characteristics ..................................................................................... 22 ?bso?ute maximum ratings ................................................................................................. ?? dc cha?acte?istics ............................................................................................................... ?? on-chi? ldo vo?tage regu?ato? cha?acte?istics ................................................................. ?? powe? consum?tion ............................................................................................................ ?? reset and su???y monito? cha?acte?istics ........................................................................... ?? exte?na? c?ock cha?acte?istics ............................................................................................. ?4 inte?na? c?ock cha?acte?istics .............................................................................................. ?5 pll cha ?acte?istics .............................................................................................................. ?6 memo?y cha?acte?istics ....................................................................................................... ?6
rev. 1.10 ? of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? table of contents table of contents i/o po?t cha?acte?istics ........................................................................................................ ?6 ?dc cha?acte?istics ............................................................................................................ ?8 operation amplifer/comparator characteristics ................................................................. ?9 gptm cha?acte?istics .......................................................................................................... ?9 i ? c cha?acte?istics ............................................................................................................... ?0 spi cha?acte?istics .............................................................................................................. ?1 5 package information ............................................................................................ 33 48-? in lqfp (7mmx7mm) out?ine dimensions ................................................................... ??
rev. 1.10 4 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? list of tables list of tables tab ?e 1. ht??f1?5x se?ies featu?es and pe?i?he?a? list ..................................................................... 14 tab ?e ?. ht??f1?5x pin desc?i?tions ................................................................................................... ?0 tab ?e ?. ?bso?ute maximum ratings ...................................................................................................... ?? tab ?e 4. dc o?e?ating conditions ......................................................................................................... ?? tab ?e 5. ldo cha?acte?istics ................................................................................................................. ?? tab ?e 6. powe? consum?tion cha?acte?istics ........................................................................................ ?? tab ? e 7. lvd/bod cha?acte?istics ......................................................................................................... ?? tab ?e 8. high s?eed exte?na? c?ock (hse) cha?acte?istics ................................................................... ?4 tab ?e 9. low s?eed exte?na? c?ock (lse) cha?acte?istics .................................................................... ?4 tab ?e 10. high s?eed inte?na? c?ock (hsi) cha?acte?istics ................................................................... ?5 tab ? e 11. low s?eed inte?na? c?ock (lsi) cha?acte?istics ..................................................................... ?5 tab ?e 1? . pll cha?acte?istics ................................................................................................................ ?6 tab ?e 1?. f?ash memo?y cha?acte?istics ................................................................................................ ?6 tab ?e 14. i/o po?t cha?acte?istics .......................................................................................................... ?6 tab ?e 15. ?dc cha?acte?istics ............................................................................................................... ?8 tab ?e 16. op ? /cmp cha?acte?istics ...................................................................................................... ?9 tab ?e 17. gptm cha?acte?istics ............................................................................................................ ?9 tab ?e 18. i ? c cha?acte?istics .................................................................................................................. ?0 tab ?e 19. spi cha?acte?istics ................................................................................................................. ?1
rev. 1.10 5 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? list of tables list of figures list of figures figu?e 1. ht??f1?5x b?ock diag?am .................................................................................................... 15 figu?e ?. ht??f1?5x memo?y ma? ....................................................................................................... 16 figu?e ?. ht??f1?5x c?ock st?uctu?e diag?am ..................................................................................... 17 figu?e 4. ht??f1? 51b 48lqfp pin ?ssignment .................................................................................. 18 figu?e 5. ht??f1?51/5?/5? 48lqfp pin ?ssignment ........................................................................... 19 figu?e 6. ?dc sam??ing netwo?k mode? ............................................................................................... ?8 figu?e 7. i ? c timing diag ?am ................................................................................................................. ?0 figu? e 8. spi timing diag?am C spi maste? mode ................................................................................ ?1 figu? e 9. spi timing diag?am C spi s?ave mode and cph?=1 ............................................................ ??
rev. 1.10 6 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? general description 1 general description the holtek ht32f125x series of device s are high performance , low power consumption 32-bit microcontrollers based on the arm ? cortex?-m3 processor core. the cortex?-m3 is a next- generation processor core which is tightly coupled with a nested vectored interrupt controller (nvic), systick timer and advanced debug support. the ht32f125x device operates at a frequency of up to 72mhz with a flash accelerator to obtain maximum efficiency. it provides up to 32kb of embedded flash memory for code/data storage and up to 8 kb of embedded sram memory for system operation and application program usage. a variety of peripherals, such as adc, i 2 c, usart, spi, sw-dp (serial wire debug port), etc., are also implemented in this device series. several power saving modes provide the fexibility for maximum optimisation between wakeup latency and power consumption , an especially important consideration in low power applications. the above features make the ht32f125x device suitable for a wide range of applications, especially in areas such as white goods and application control, power monitor and alarm systems, consumer and handheld equipment, data logg ing applications and so on.
rev. 1.10 7 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? general description features 2 features core ? 32-bit arm ? cortex?-m3 processor core ? up to 72mhz operation frequency ? 1.25 dmips/mhz (dhrystone 2.1) ? single-cycle multiplication and hardware division ? integrated nested vectored interrupt controller (nvic) ? 24-bit systick timer the cortex?-m3 processor is a general-purpose 32-bit processor core especially suitable for products requiring high performance and low power consumption microcontrollers. it offers many new features such as a thumb-2 instruction set, hardware divider, low latency interrupt respond time, atomic bit-banding access and multiple buses for simultaneous accesses. the cortex?-m3 processor is based on the armv7 architecture and supports both thumb and thumb-2 instruction sets. some system peripherals listed below are also provided by cortex?-m3: ? internal bus matrix connected with icode bus, dcode bus, system bus, private peripheral bus (ppb) and debug accesses (ahb-ap) ? nested vectored interrupt controller (nvic) ? flash patch and breakpoint (fpb) ? data watchpoint and trace (dwt) ? instrument trace macrocell (itm) ? memory protection unit (mpu) ? serial wire debug port (sw-dp) ? embedded trace macrocell (etm) ? trace port interface unit (tpiu) on-chip memory ? 9 to 32 kb on-chip flash memory for instruction/data and option storage ? 2 to 8 kb on-chip sram ? supports several boot modes the arm ? cortex?-m3 processor is structured in harvard architecture which can use separate buses to fetch instructions and load/store data. the instruction code and data are both located in the same memory address space but in different address ranges. the maximum address range of the cortex?-m3 is 4gb since it has a 32-bit bus address width. additionally , a pre-defned memory map is provided by the cortex?-m3 processor to reduce the software complexity of repeated implementation of different device vend ors . however, some regions are used by the arm ? cortex?-m3 system peripherals. r efer to the arm ? cortex?-m3 technical reference manual for more information. the figure 2. ht32f125x memory map shows the memory map of the ht32f125x series of devices , including code, sram, peripheral, and other pre-defned regions.
rev. 1.10 8 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? features flash memory controller ? flash accelerator for maximum effciency ? 32-bit word programming (isp and iap) ? flash protection capability to prevent illegal access the flash memory controller , fmc , provides all the necessary functions and pre-fetch buffer for the embedded on-chip flash memory. since the access speed of the flash memory is slower than the cpu, a wide access interface with a pre-fetch buffer is provided for the flash memory in order to reduce the cpu wait ing time which will cause cpu instruction execution delays . flash memory word program/page erase functions are also provided . reset control unit ? supply supervisor: power on reset (por) brown out detector (bod) programmable low voltage detector (lvd) the reset control unit (rstcu) has three kinds of reset, the power on reset, system reset and apb unit reset. the power on reset, known as a cold reset, resets the full system during power up. a system reset resets the processor core and peripheral ip components with the exception of the sw-dp controller. the resets can be triggered by an external signal, internal events and the reset generators. clock control unit ? external 4 to 16 mhz crystal oscillator ? external 32,768 hz crystal oscillator ? internal 8mhz rc oscillator trimmed to 1% accuracy at 3.3v operating voltage and 25c oper - ating temperature ? internal 32khz rc oscillator ? integrated system clock pll ? independent clock gating bits for peripheral clock sources the clock control unit, ckcu, provides a range of oscillator and clock functions. these include a high speed internal rc oscillator (hsi), a high speed external crystal oscillator (hse), a low speed internal rc oscillator (lsi), a low speed external crystal oscillator (lse), a phase lock loop (pll), a hse clock monitor, clock prescalers, clock multiplexers and clock gating circuitry. the clocks of the ahb, apb and cortex tm -m3 are derived from the system clock (ck_sys) which can come from the hsi, hse or pll. the watchdog timer and real time clock (rtc) use either the lsi or lse as their clock source. the maximum operating frequency of the system core clock (ck_ahb) can be up to 72mhz. ( note: lse is not supported by ht32f1251b).
rev. 1.10 9 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? features features power management ? single 3.3v power supply: 2.7v to 3.6v ? integrated 1.8v ldo regulator for core and peripheral power supply ? v b at battery power supply for rtc and backup registers ? three power domains: 3.3v, 1.8v and backup ? four power saving modes: sleep, deep-sleep1, deep-sleep2, power-down the power consumption can be regarded as one of the most important issues for many embedded system applications. accordingly the power control unit, pwrcu, in these devices provides many types of power saving modes such as sleep, deep-sleep1, deep-sleep2 and power-down mode. these operating modes reduce the power consumption and allow the application to achieve the best trade-off between the conficting demands of cpu operating time, speed and power consumption. ( note: ht32f1251b does not support v bat battery power supply). analog to digital converter ? 12-bit sar adc engine ? up to 1 msps conversion rate - 1 s at 56mhz, 1.17s at 72mhz ? 8 external analog input channels ? supply voltage range: 2.7v ~ 3.6v ? conversion range: v ssa ~ v dda a 12-bit multi-channel adc is integrated in the device. there are a total of 10 multiplexed channels , which include 8 external channels on which the external analog signals can be measured , and 2 internal channels . if the input voltage is required to remain within a specific threshold window, the analog watchdog function will monitor and detect the signal. an interrupt will then be generated to inform that the input voltage is higher or lower than the set thresholds. there are three conversion modes to convert an analog signal to digital data. the adc can be operated in one shot, continuous and discontinuous conversion mode s . analog operational amplifer/comparator ? 2 operational amplifers or 2 comparator functions which are software confgurable ? supply voltage range: 2.7v ~ 3.6v two operational amplifers/comparators (opa/cmp) are implemented within the devices. they can be confgured either as operational amplifers or as analog comparators. when confgured as comparators, they are capable of asserting interrupts to the nvic.
rev. 1.10 10 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? features i/o ports ? up to 32 gpios ? port a and port b are mapped as 16 external interrupts (exti) ? almost all i/o pins are 5 v-tolerant except for pins shared with analog inputs there are up to 32 general purpose i/o pins , (gpio), named pa0 ~ pa15 and pb0 ~ pb15 for the device to implement logic input/output functions. each of the gpio ports has related control and confguration registers to satisfy the requirements of specifc applications. the gpio ports are pin-shared with other alternat ive functions (afs) to obtain maximum fexibility on the package pins . the gpio pins can be used as alternat ive functional pins by confguring the corresponding registers regardless of the af input or output pins. the external interrupts on the gpio pins of the device have related control and configuration registers in the external interrupt control unit (exti). pwm generation and capture timers ? two 16-bit general-purpose timers (gptm) ? up to 4chs pwm compare output or input capture for each gptm ? external trigger input the general-purpose timers, known as gptm0 and gptm1, consist of one 16-bit up/down-counter, four 16-bit capture/compare registers (ccrs), one 16-bit counter-reload register (crr) and several control/status registers. they can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as single pulse generation or pwm output. the gptm supports an encoder interface using a decoder with two inputs.
rev. 1.10 11 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? features features watchdog timer ? 12-bit down counter with 3-bit prescaler ? interrupt or reset event for the system ? programmable watchdog timer window function ? write protection function the watchdog timer is a hardware timing circuitry that can be used to detect system failure s due to software malfunctions . it includes a 12-bit down-counting counter, a prescaler, a wdt counter value register, a wdt delta value register, interrupt related circuits, wdt operation control circuitry and the wdt protection mechanism. the watchdog timer can be operated in an interrupt mode or a reset mode. the watchdog timer will generate an interrupt or a reset when the counter counts down and reaches a zero value . if the software does not reload the counter value before the watchdog timer underfow occurs, an interrupt or a reset will be generated when the counter underfows. in addition, an interrupt or reset is also generated if the software reloads the counter when the counter value is greater than or equal to the wdt delta value. that means the counter must be reloaded within a limited timing window using a specifc method. the watchdog timer counter can be stopped while the processor is in the debug mode. the register write protection function can be enabled to prevent it from changing the configuration of the watchdog timer unexpectedly. real time clock ? 32-bit up-counter with a programmable prescaler ? alarm function ? interrupt and wake-up event the real time clock , rtc , circuitry includes the apb interface, a 32-bit up-counter, a control register, a prescaler, a compare register and a status register. most of the rtc circuits are located in the backup domain except for the apb interface. the apb interface is located in the v dd18 domain. therefore, it is necessary to be isolated from the iso signal that comes from the power control unit when the v dd18 domain is powered off, i.e., when the device enters the power-down mode. the rtc counter is used as a wakeup timer to generate a system resume from the power-down mode.
rev. 1.10 1? of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? features inter-integrated circuit (i 2 c) ? support both master and slave mode with a frequency of up to 400 khz ? provide arbitration function ? support s 7-bit and 10-bit addressing mode and general call addressing the i 2 c module is an internal circuit allowing communication with an external i 2 c interface which is an industry standard two line serial interface used for connection to external hardware. these two serial lines are known as a serial data line , sda , and a serial clock line , scl. the i 2 c module provides two data transfer rates: (1) 100 khz in the standard mode or (2) 400 khz in the fast mode. t he scl period generation register is used to setup different kinds of duty cycle implement ation for the scl pulse. the sda line which is connected to the whole i 2 c bus is a bi-directional data line between the master and slave devices used for the transmi ssion and reception of data. the i 2 c module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the i 2 c bus at the same time . serial peripheral interface (spi) ? spi interfaces with a frequency of up to 18 mhz ? support both master and slave mode ? fifo depth: 8 levels ? multi-master and multi-slave operation the serial peripheral interface , spi , provides an spi protocol data transmit and receiv e function in both master and slave mode. the spi interface uses 4 pin s, among which are the serial data input and output lines miso and mosi, the clock line , sck , and the slave select line , sel. one spi device acts as a master which controls the data fow using the sel and sck signals to indicate the start of the data communication and the data sampling rate. to receive a data byte, the stream ed data bits are latched on a specifc clock edge and stored in the data register or in the rx fifo. data transmission is carried in a similar way but with a reverse sequence. the mode fault detection provides a capability for multi-master application s .
rev. 1.10 1? of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? features features universal synchronous asynchronous receiver transmitter (usart) ? operating frequency: up to 4.5mhz ? supports both asynchronous and clocked synchronous serial communication modes ? irda sir encoder and decoder ? rs485 mode with output enable control ? full modem function ? fifo depth: 16 x 9 bits for both receiver and transmitter the universal synchronous asynchronous receiver transceiver , usart , provides a flexible full duplex data exchange using synchronous or asynchronous transfer. the usart is used to translate data between parallel and serial interface s , and is also commonly used for rs232 standard communication. the usart peripheral function supports fve-type s of interrupt including line status interrupt, transmitter fifo empty interrupt, receiver threshold level reaching interrupt, time out interrupt and modem status interrupt. the usart module includes a 16-byte transmitter fifo , (tx_fifo) and a 16-byte receiver fifo (rx_fifo). software can detect a usart error status by reading the line status register , lsr. the status includes the type and the condition of transfer operations as well as several error conditions result ing from parity, overrun, framing and break events. the usart includes a programmable baud rate generator which is capable of dividing the ck_ahb to produce a clock for the usart transmitter and receiver. debug support ? serial wire debug port - sw-dp ? 6 instruction comparators and 2 literal comparators for hardware breakpoint or code / literal patch ? 4 comparators for hardware watchpoint ? 1-bit asynchronous trace - traceswo package and operation temperature ? 48-pin lqfp package ? operation temperature range: -40 c to +85 c
rev. 1.10 14 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? overview 3 overview device information most features are common to all devices while the main features distinguishing them are flash memory and sram memory capacities. table 1. ht32f125x series features and peripheral list peripherals ht32f1253 ht32f1252 ht32f1251 ht32f1251b main f?ash (kb) ?1 16 8 8 o?tion bytes f?ash (kb) 1 1 1 1 sr?m (kb) 8 4 ? ? time ?s gptm ? rtc 1 wdt 1 communication us? rt 1 spi 1 i ? c 1 gpio ?? ?0 exti 16 1?-bit ?dc numbe? of channe?s 1 8 channe?s op ?/com?a?ato? ? cpu f?equency u? to 7? mhz o?e?ating vo?tage ?.7 v ~ ?.6 v o?e?ating tem?e?atu?e -40 ~ +85 package lqfp48
rev. 1.10 15 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? overview overview block diagram tpiu sw - dp tr?ceswo swdio swclk ? p b 1 ? p b 0 ?hb pe?i?he?a?s f?ash memo?y i c o d e d c o d e co?tex tm - m ? p?ocesso? f max : 7? mhz s y s t e m ?hb to ?pb b?idge nvic sr?m sr?m cont?o??e? fmc cont?o? registe?s ckcu / rstcu cont?o? registe?s s?ave s?ave s?ave i n t e ? ? u ? t ? e q u e s t 1? -bit s?r ?dc ?na?og op? /cmp powe?ed by v dd? vdd? vss? cn0 ? cp 0 ?out 0 cn1 ? cp 1 ?out 1 us?rt spi ?dc op? /cmp gpio? gpiob ?fio exti i? c wdt gptm0 gptm1 porb v b?k ? . ? v lsi ?? khz lse ??? 768 hz breg powe?ed by v b?k vldoin vb?t v b?k pwrsw rtc pwrcu pb [ 15 : 0 ] p? [ 15: 0 ] ur_ tx ? ur_ rx ur _ dcd ur_ dsr ur _ dtr ur_ ri ur_ rts / txe ur_ cts / sck spi _ mosi spi _ miso spi _ sck spi _ sel ?dc _ in 0 . . . ?dc _ in 7 nrst i ? c _ sd? i ? c _ scl powe?ed by ? . ? v pll f max : 144 mhz por 1 . 8 v rtcout w?keup boot 0 boot 1 f?ash memo?y cont?o??e? c ? o ck a n d ? e se t co n t ? o ? xt?l ?? kin xt?l ?? kout bod lvd xt?lin xt?lout vldoout vdd 18 hsi 8 mhz hse 4 ~ 16 mhz p o w e ? co n t ? o ? b u s m at?ix powe?ed by 1 . 8 v ? f ? f ? f ? f ?f ?f ?f ? f ? f ? f ? f ? f ? f ?f powe? su???y : bus : cont?o? signa? : ??te?nate function : ldo 1 . 8 v ?f powe?ed by 1 . 8 v gt 0 _ ch0 gt 0 _ ch? gt 0 _ eti . . . gt 1 _ ch0 gt 1 _ ch? gt 1 _ eti . . . maste? vldoin vssldo note: ht??f1?51b does not inc?ude the vb? t ? xt ?l??kin and xt ?l?? kout ?ins. figure 1. ht32f125x block diagram
rev. 1.10 16 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? overview memory map rese?ved p?ivate ?e?i?he?a? bus rese?ved ?pb/?hb bit band a?ias rese?ved 0xffff_ffff 0xe010_0000 0xe000_0000 0x4400_0000 0x4?00_0000 0x4010_0000 ?hb ?e?i?he?a?s ?pb ?e?i?he?a?s 0x4008_0000 0x4000_0000 rese?ved 0x??04_0000 sr?m bit band a?ias 0x??00_0000 rese?ved 0x?000_?000 4 kb on-chi? sr?m 0x?000_1000 ? kb on-chi? sr?m ? kb on-chi? sr?m 0x?000_0800 0x?000_0000 rese?ved 0x1ff0_0400 o?tion bytes f?ash 0x1ff0_0000 rese?ved 0x1f00_0800 boot loade? 0x1f00_0000 rese?ved 0x0000_7c00 15 kb on-chi? f?ash 8 kb on-chi? f?ash 8 kb on-chi? f?ash 0x0000_0000 code sr?m pe?i?he?a?s 51? kb 51? kb ?? mb ?56 kb 8 kb 4 kb ? kb 1 kb ? kb ht??f1?5? ht??f1?5? ht??f1?51(b) ?1 kb 16 kb 8 kb ht??f1?5? ht??f1?51(b) ckcu/rstcu rese?ved 0x4008_?000 0x4010_0000 0x4008_8000 rese?ved fmc 0x4008_?000 0x4008_0000 gptm1 rese?ved 0x4007_0000 0x4006_f000 gptm0 0x4006_e000 rese?ved 0x4006_b000 rtc/pwrcu 0x4006_?000 rese?ved 0x4006_9000 wdt 0x4006_8000 rese?ved 0x4004_9000 i ? c 0x4004_8000 rese?ved 0x400?_5000 exti 0x400?_4000 rese?ved 0x400?_?000 ?fio 0x400?_?000 rese?ved 0x4001_c000 gpio b 0x4001_b000 gpio ? 0x4001_?000 rese?ved 0x4001_9000 op?/cmp 0x4001_8000 rese?ved 0x4001_1000 ?dc 0x4001_0000 rese?ved 0x4000_5000 spi 0x4000_4000 rese?ved 0x4000_1000 us?rt 0x4000_0000 ?hb pe?i?he?a?s ?pb pe?i?he?a?s 0x0000_?000 0x0000_4000 ht??f1?5? notes: 1. fo? ht??f1?51(b)? the f?ash memo?y s?ace at 0x0000_?000 to 0x0000_7bff and the sr? m memo?y s?ace at 0x?000_0800 to 0x?000_1fff a?e ?ese?ved. 2. fo? ht??f1?5?? the f?ash memo?y s? ace at 0x0000_4000 to 0x0000_7bff and the sr?m memo?y s?ace at 0x?000_1000 to 0x?000_1fff a?e ?ese?ved. figure 2. ht32f125x memory map
rev. 1.10 17 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? overview overview clock structure 4-16 mhz hse xt?l 8 mhz hsi rc ?? khz lsi rc ??.768 khz lse osc wdtsrc pllsrc ?hb p?esca?e? 1???4?8 fclk ( f?ee ?unning c?ock) hclkc ( to co?tex-m?) stclk (to systick) ?dc p?esca?e? 1???4?6?8... ck_?dc f ck_ahb,max = 72mhz ck_wdt wdten ck_pll/16 ck_hsi/16 ck_hse/16 ck_sys/16 ckout ckoutsrc[?:0] hseen hsien lseen lsien f ck_sys,max = 144mhz ck_lsi ck_lse ck_?hb/16 ck_hsi ck_hse pclk ( to op?? ?fio gpio po?t? ?dc? spi? us?rt? i?c? gptim? exti? rtc? wdt) 14 pll c?ock monito? pllen ck_us?rt ck_lse ck_pll uren cm?en (cont?o? by hw) op?0en wdten (?pb ?e?i?he?a?s c?ock gating) ?dcen p?esca?e? 1? ? f ck_pll,max = 144mhz ck_lsi hclks ( to sr?m) hclkf ( to f?ash) cm?en fmcen cm?en sr?men 14 1 0 rtcsrc ck_rtc rtcen 1 0 1 0 ck_?hb 000 001 010 011 100 101 110 ck_sys sw[1:0] 0x 11 10 8 legend: hse = high s?eed exte?na? c?ock hsi = high s?eed inte?na? c?ock lse = low s?eed exte?na? c?ock lsi = low s?eed inte?na? c?ock notes: 1. cont?o? bits lsien & lseen a?e ? ocated at rtc cont?o? registe? (rtccr). 2. ht??f1?51b does not inc?ude the vb? t ? xt ?l??kin and xt ?l?? kout ?ins. figure 3. ht32f125x clock structure diagram
rev. 1.10 18 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? overview pin assignment 48 47 46 45 44 4? 4? 41 40 ?9 ?8 1 ? ? 4 5 6 7 8 9 10 11 1? 14 15 16 17 18 19 ?0 ?1 ?? ?? ?5 ?4 ?? ?? ?1 ?0 ?9 ?8 ?7 ?6 ?5 pa0 adc_in0 gt1_eti pa1 adc_in1 - gt0_ch3 pa2 adc_in2 ur_dcd gt0_ch2 pa3 adc_in3 ur_dsr gt0_ch1 pa4 adc_in4 ur_dtr gt0_ch0 pa5 adc_in5 ur_ri spi_mosi pa6 adc_in6 ur_rts /txe spi_miso pa7 adc_in7 ur_cts /sck spi_sck pa8 - ur_rx spi_sel pa9- boot0 - ur_tx - pa10- boot1 - - - - - pb1 xtalout - - pb0 xtalin gt1_ch0 ur_ri spi_mosi pb15 gt1_ch1 ur_dtr spi_miso pb14 gt1_ch2 ur_dsr spi_sck pb13 gt1_ch3 ur_dcd spi_sel pb12 v ss33_2 v dd33_2 gt0_ch0 - pa15 trace swo gt0_ch1 - pa14 swclk gt0_ch2 - pa13 swdio n.c. af0 (default) af1 af2 af3 af1 af2 af3 af0 (default) af1 af2 af3 af0 (default) af1 af2 af3 - v ldoin v ssldo nrst n.c. n.c. n.c. rtcout pb10- wakeup - - - - - - gt0_eti gt0_ch3 pb11 pa11 pa12 ckout i2c_scl i2c_sda v ssa_1 pb7 v dda v ss33_1 v dd33_1 pb6 pb5 pb4 pb3 pb2 v dd18 cn0 cp0 aout0 cn1 cp1 aout1 - - ur_rts /txe ur_cts /sck - - gt0_et1 gt1_eti gt1_ch3 gt1_ch2 gt1_ch1 gt1_ch0 p?? p?? 5vt 5vt 5vt 5vt 5vt ??v ??v 5vt 5vt 5vt 5vt p?? p?? 5vt 5vt 5vt p18 5vt 5vt 5vt ??v ??v ??v ??v ??v ??v ??v ??v ??v ??v ??v ??v ??v ??v p?? p?? ?p ?p p18 p?? ?p p18 ??v 5vt 5vt 3.3 v digital power pad 3.3 v analog power pad 1.8 v power pad 3.3 v i/o pad 5 v tolerance i/o pad high current output 5 v tolerance i/o pad holtek ht32f1251b lqfp48 ?7 1? ?4 ?6 v ssa_2 ?p p?? v ss33_3 n.c. af0 (default) v ldoout figure 4. ht32f1251b 48lqfp pin assignment
rev. 1.10 19 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? overview overview 48 47 46 45 44 4? 4? 41 40 ?9 ?8 1 ? ? 4 5 6 7 8 9 10 11 1? 14 15 16 17 18 19 ?0 ?1 ?? ?? ?5 ?4 ?? ?? ?1 ?0 ?9 ?8 ?7 ?6 ?5 pa0 adc_in0 gt1_eti pa1 adc_in1 - gt0_ch3 pa2 adc_in2 ur_dcd gt0_ch2 pa3 adc_in3 ur_dsr gt0_ch1 pa4 adc_in4 ur_dtr gt0_ch0 pa5 adc_in5 ur_ri spi_mosi pa6 adc_in6 ur_rts /txe spi_miso pa7 adc_in7 ur_cts /sck spi_sck pa8 - ur_rx spi_sel pa9- boot0 - ur_tx - pa10- boot1 - - - - - pb1 xtalout - - pb0 xtalin gt1_ch0 ur_ri spi_mosi pb15 gt1_ch1 ur_dtr spi_miso pb14 gt1_ch2 ur_dsr spi_sck pb13 gt1_ch3 ur_dcd spi_sel pb12 v ss33_2 v dd33_2 gt0_ch0 - pa15 trace swo gt0_ch1 - pa14 swclk gt0_ch2 - pa13 swdio n.c. af0 (default) af1 af2 af3 af1 af2 af3 af0 (default) af1 af2 af3 af0 (default) af1 af2 af3 - v ldoin v ssldo nrst v bat xtal32k in xtal32k out pb8 pb9 rtcout pb10- wakeup - - - - - - gt0_eti gt0_ch3 pb11 pa11 pa12 ckout i2c_scl i2c_sda - - - - v ssa_1 pb7 v dda v ss33_1 v dd33_1 pb6 pb5 pb4 pb3 pb2 v dd18 cn0 cp0 aout0 cn1 cp1 aout1 - - ur_rts /txe ur_cts /sck - - gt0_et1 gt1_eti gt1_ch3 gt1_ch2 gt1_ch1 gt1_ch0 p?? p?? 5vt p?? ??v ??v 5vt 5vt 5vt 5vt ??v ??v 5vt 5vt 5vt 5vt p?? p?? 5vt 5vt 5vt p18 5vt 5vt 5vt ??v ??v ??v ??v ??v ??v ??v ??v ??v ??v ??v ??v ??v ??v p?? p?? ?p ?p p18 p?? ?p p18 ??v 5vt 5vt 3.3 v digital power pad 3.3 v analog power pad 1.8 v power pad 3.3 v i/o pad 5 v tolerance i/o pad high current output 5 v tolerance i/o pad holtek ht32f1251/52/53 lqfp48 ?7 1? ?4 ?6 v ssa_2 ?p p?? v ss33_3 n.c. af0 (default) v ldoout figure 5. ht32f1251/52/53 48lqfp pin assignment
rev. 1.10 ?0 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? overview table 2. ht32f125x pin descriptions pin name pins type (note1) io level (note2) description 48 lqfp default function (af0) af1 af2 af3 v ss?_? 1 p g?ound ?efe?ence fo? ?dc and op ?/com?a?ato? p? 0 ? i/o gpio p ?0 ?dc_in0 gt1_eti gt0_ch? p? 1 ? i/o gpio p ?1 ?dc_in1 gt0_ch? p ?? 4 i/o gpio p ?? ?dc_in? ur_dcd gt0_ch1 p ?? 5 i/o gpio p ?? ?dc_in? ur_dsr gt0_ch0 p? 4 6 i/o gpio p ?4 ?dc_in4 ur_dtr spi_mosi p? 5 7 i/o gpio p ?5 ?dc_in5 ur_ri spi_miso p? 6 8 i/o gpio p ?6 ?dc_in6 ur_rts/txe spi_sck p? 7 9 i/o gpio p ?7 ?dc_in7 ur_cts/sck spi_sel p? 8 10 i/o 5v-t gpio p ?8 ur_rx p? 9 11 i/o 5v-t gpio p ?9-boot0 ur_tx p ?10 1? i/o 5v-t gpio p ?10-boot1 v ldoout 1? p ldo 1.8 v output. please put a 10f capacitor to gnd in those pins as c?ose as ?ossib?e. n.c 14 v ldoin 15 p ldo ?.? v ?owe? sou?ce? a?so connected to the ?owe? switch of the backu? domain. v ssldo 16 p ldo g?ound ?efe?ence nrst 17 i (backu? domain) 5v-t exte?na? ?eset ?in and exte?na? wakeu? ?in in powe?-down mode v b ?t (note?) 18 p vdd ?.? v fo? backu? domain pb8 (note?) 19 i/o (backu? domain) xt ?l??kin pb8 pb9 (note?) ?0 i/o (backu? domain) xt ?l??kout pb9 pb10 ?1 i/o (backu? domain) 5v-t rtcout pb10- w ?keup gt0_eti pb11 ?? i/o 5v-t gpio pb11 ckout gt0_ch? p? 11 ?? i/o 5v-t gpio p ? 11 i?c_scl p ?1? ?4 i/o 5v-t gpio p ?1? i?c_sd? p ?1? ?5 i/o 5v-t swdio p ?1? gt0_ch? p ?14 ?6 i/o 5v-t swclk p ?14 gt0_ch1 p ?15 ?7 i/o 5v-t tr?ceswo p ?15 gt0_ch0 v dd??_? ?8 p ?.? v vo?tage fo? digita? i/o v ss??_? ?9 p g?ound ?efe?ence fo? digita? i/o v ss??_? ?0 p g?ound ?efe?ence fo? digita? co?e pb1? ?1 i/o 5v-t gpio pb1? spi_sel ur_dcd gt1_ch?
rev. 1.10 ?1 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? overview overview pin name pins type (note1) io level (note2) description 48 lqfp default function (af0) af1 af2 af3 pb1? ?? i/o 5v-t gpio pb1? spi_sck ur_dsr gt1_ch? pb14 ?? i/o 5v-t gpio pb14 spi_miso ur_dtr gt1_ch1 pb15 ?4 i/o 5v-t gpio pb15 spi_mosi ur_ri gt1_ch0 pb0 ?5 i/o xt ?lin pb0 pb1 ?6 i/o xt ?lout pb1 v dd18 ?7 p 1.8 v vo?tage fo? co?e n.c ?8 pb? ?9 i/o gpio pb? cn0 gt1_ch0 pb? 40 i/o gpio pb? cp0 gt1_ch1 pb4 41 i/o gpio pb4 ?out0 ur_rts/txe gt1_ch? pb5 4? i/o gpio pb5 cn1 gt1_ch? pb6 4? i/o gpio pb6 cp1 gt1_eti pb7 44 i/o gpio pb7 ?out1 ur_cts/sck gt0_eti v dd??_1 45 p ?.? v vo?tage fo? digita? i/o v ss??_1 46 p g?ound ?efe?ence fo? digita? i/o v dd? 47 p ?.? v ana?og vo?tage fo? ?dc and op ?/com?a?ato? v ss?_1 48 p g?ound ?efe?ence fo? ?dc and op ?/com?a?ato? notes: 1. i = in?ut? o = out?ut? p = ?owe? su??? y. 2. 5v-t = 5v to ?e?ant. 3. ht??f1?51b does not inc?ude the vb? t ? xt ?l??kin and xt ?l?? kout ?ins. 4. the gpios a ?e in ?f0 state afte? vdd18 ?owe? on ?eset (por) exce? t the rtcout ? in of backu? domain i/o. the rtcout ?in is ? eset by the backu? domain ?owe?-on-? eset (porb) o? backu? domain softwa?e ?eset (b? k_rst bit in b?k_cr ?egiste?). 5. the backu ? domain of i/o ?ins has d?iving cu??ent ca?abi?ity ?imitation (< 1m? @ v b ?t = ?.?v).
rev. 1.10 ?? of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? electrical characteristics 4 electrical characteristics absolute maximum ratings the following table shows the absolute maximum ratings of the device. these are stress ratings only. stresses beyond absolute maximum ratings may cause permanent damage to the device. note that the device is not guaranteed to operate properly at the maximum ratings. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. table 3. absolute maximum ratings symbol parameter min max unit v dd?? exte?na? main su???y vo?tage v ss - 0.? v ss + ?.6 v v dd? exte?na? ana?og su???y vo?tage v ss? - 0.? v ss? + ?.6 v v b ?t exte?na? batte?y su???y vo?tage v ss - 0.? v ss + ?.6 v v ldoin exte?na? ldo su???y vo?tage v ss - 0.? v ss + ?.6 v v in in?ut vo? tage on 5v-to?e?ant i/o v ss - 0.? v ss + 5.5 v in?ut vo?tage on othe? i/o v ss - 0.? v dd?? + 0.? v t ? ?mbient o?e?ating tem?e?atu?e ?ange -40 +85 c t stg sto?age tem?e?atu?e ?ange -55 +150 c t j maximum junction tem?e?atu?e 1?5 c p d tota ? ?owe? dissi?ation 500 mw v esd e?ect?ostatic discha?ge vo?tage (human body mode) -4000 +4000 v dc characteristics table 4. dc operating conditions ta = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit v dd?? o?e?ating vo?tage of i/o ?.7 ?.? ?.6 v v dd? ?na?og o?e?ating vo?tage ?.7 ?.? ?.6 v v b ?t o?e?ating vo?tage of batte?y su???y ?.7 ?.? ?.6 v v ldoin ldo o?e?ating vo?tage ?.7 ?.? ?.6 v v dd18 o?e?ating vo?tage of co?e ?owe? 1.6? 1.8 1.98 v on-chip ldo voltage regulator characteristics table 5. ldo characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit v ldoout inte?na? ?egu?ato? out?ut vo?tage v ldoin = ?.?v regu?ato? in?ut 1.71 1.8 1.89 v i dd18 out?ut cu??ent v ldoin = ?.4v regu?ato? in?ut ?00 m? c ldo external flter capacitor value for inte?na? co?e ?owe? su???y the ca?acito? va?ue is de?endent on the co?e ?owe? cu??ent consum?tion ?.? 10 f
rev. 1.10 ?? of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? electrical characteristics electrical characteristics power consumption table 6. power consumption characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit i dd su???y cu??ent (run mode) v dd?? = v b ?t = ?.?v ? hse = 8mhz? pll = 144mhz? f hclk = 7?mhz? f pclk = 7?mhz? ??? ?e?i?he?a?s enab?ed 47 m? v dd?? = v b ?t = ?.?v ? hse = 8mhz? pll = 144mhz? f hclk = 7?mhz? f pclk = 7?mhz? ??? ?e?i?he?a?s disab?ed ?8 m? su???y cu??ent (s?ee? mode) v dd = v b ?t = ?.?v ? hse = 8mhz? pll = 144mhz? f hclk = 0mhz? f pclk = 7?mhz? ??? ?e?i?he?a?s enab?ed ?0 m? v dd?? = v b ?t = ?.?v ? hse = 8mhz? pll = 144mhz? f hclk = 0mhz? f pclk = 7?mhz? ??? ?e?i?he?a?s disab?ed 7 m? su???y cu??ent (dee?-s?ee?1 mode) v dd?? = v b ?t = ?.?v ? ??? c? ock off (hse/pll/f hclk )? ldo in ?ow ?owe? mode , lsi on? rtc on 66 a su???y cu??ent (dee?-s?ee?? mode) v dd?? = v b ?t = ?.?v ? ??? c? ock off (hse/pll/f hclk )? ldo off (dmos on) , lsi on? rtc on 11 a su???y cu??ent (powe?-down mode) v dd?? = v b ?t = ?.?v ? ldo off? lse on? lsi off? rtc on 4.? a v dd?? = v b ?t = ?.?v ? ldo off? lse on? lsi off? rtc off 4.1 a v dd?? = v b ?t = ?.?v ? ldo off? lse off? lsi on? rtc on 4.? a v dd?? = v b ?t = ?.?v ? ldo off? lse off? lsi on? rtc off 4.? a i b ?t batte?y su???y cu??ent (powe?- down mode) v dd?? not ??esent? v b ?t = ?.?v ? ldo off? lse off? lsi on? rtc on 4 a v dd?? not ??esent? v b ?t = ?.?v ? ldo off? lse off? lsi on? rtc off ?.9 a notes: 1. hse is the high s?eed exte?na? osci??ato? whi?e hsi is the 8mhz high s?eed inte?na? osci??ato? . 2. lse is the ?ow s?eed exte?na? osci??ato? whi?e lsi is the ??khz ?ow s?eed inte?na? osci??ato? . 3. rtc means ?ea? time c?ock. 4. code = whi? e (1) { nop x n } executed in f?ash (n > ?00). reset and supply monitor characteristics table 7. lvd/bod characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit v bod vo ?tage of b?own out detecto? ?.5 v v lvd vo ? tage of low vo?tage detecto? lvds (note1) = 00 ?.7 v lvds (note1) = 01 ?.8 v lvds (note1) = 10 ?.9 v lvds (note1) = 11 ?.0 v v por vo ?tage of powe? on reset 1.?6 v note: lvds feld is in pwrcu lvdcsr register
rev. 1.10 ?4 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? electrical characteristics external clock characteristics table 8. high speed external clock (hse) characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit f hse high s?eed exte?na? osci??ato? f?equency (hse) v dd?? = ?.?v 4 16 mhz c hse recommended ?oad ca?acitance on xt ?lin and xt ?lout tbd ?f r fhse recommended exte?na? feedback ?esisto? between xt ?lin and xt ?lout 1.0 m d hse hse osci??ato? duty cyc?e 40 60 % i ddhse hse osci??ato? o?e?ating cu??ent v dd?? = ?.?v ? t ? = ?5c 0.96 m? i stbhse hse osci??ato? standby cu??ent v dd?? = ?.?v ? t ? = ?5c 0.1 a t suhse hse osci??ato? sta?tu? time v dd?? = ?.?v ? t ? = ?5c 4 ms table 9. low speed external clock (lse) characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit f lse low s?eed exte?na? osci??ato? f?equency (lse) v dd?? = v b ?t = ?.?v ??.768 khz c lse recommended ?oad ca?acitance on xt ?l??kin and xt ?l?? kout ?ins tbd ?f r flse recommended exte?na? feedback ?esisto? between xt ?l??kin and xt ?l?? kout ?ins 10 m d lse lse osci??ato? duty cyc?e 40 60 % i ddlse lse osci??ato? o?e?ating cu??ent v dd?? = v b ?t = ?.?v ? lsesm = 0 (no?ma? sta?tu? mode) 1.7 a i stblse lse osci??ato? standby cu??ent v dd?? = v b ?t = ?.?v ? lsesm = 1 (fast sta?tu? mode) ? 8 a t sulse lse osci??ato? sta?tu? time v dd?? = v b ? t = ?.?v ? lsesm = 1 (fast sta?tu? mode) ?00 ms
rev. 1.10 ?5 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? electrical characteristics electrical characteristics internal clock characteristics table 10. high speed internal clock (hsi) characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit f hsi high s?eed inte?na? osci??ato? f?equency (hsi ) v dd?? = ?.?v ? t ? = -40c ~ +85c tbd 8 tbd mhz ?cc hsi hsi osci??ato? f?equency accu?acy facto?y-t?immed? v dd?? = ?.?v ? t ? = ?5c -1 +1 % d hsi hsi osci??ato? duty cyc?e v dd?? = ?.?v ? f hsi = 8mhz ?5 65 % i ddhsi hsi osci??ato? o?e?ating cu??ent v dd?? = ?.?v ? f hsi = 8mhz 0.9? m? t suhsi hsi osci??ato? sta?tu? time v dd?? = ?.?v ? f hsi = 8mhz? hsircbl = 0 (hsi ready counte? bits length 7 bits ) 17 s note: hsircbl feld is in pwrcu hsircr register table 11. low speed internal clock (lsi) characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit f lsi low s?eed inte?na? osci??ato? f?equency(lsi) v dd?? = v b ?t = ?.?v ? t ? = -40 c ~ +85c ?5 ?? 4? khz i ddlsi lsi osci??ato? o?e?ating cu??ent v dd?? = v b ?t = ?.?v ? t ? = ?5 c 1.0 ? a t sulsi lsi osci??ato? sta?tu? time v dd?? = v b ?t = ?.?v ? t ? = ?5 c ?5 ms
rev. 1.10 ?6 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? electrical characteristics pll characteristics table 12. pll characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit f pllin pll in ?ut c?ock f?equency pllv dd18 = 1.8v 4 16 mhz f pll pll out ?ut c?ock f?equency pllv dd18 = 1.8v 8 144 mhz t lock pll ?ock time pllv dd18 = 1.8v tbd ms memory characteristics table 13. flash memory characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit n endu numbe? of gua?anteed ??og?am /e?ase cyc?es befo?e fai?u?e. (endu?ance) v dd18 =1.8v ? t ? = -40c ~ +85c 1 kcyc?es t ret data ?etention time t ? = ?5c 100 yea ?s t prog wo ?d ??og?amming time v dd18 = 1.8v ? t ? = -40c ~ +85c 40 s t er?se page e?ase time v dd18 = 1.8v ? t ? = -40c ~ +85c ?0 40 ms t mer?se mass e?ase time v dd18 = 1.8v ? t ? = -40c ~ +85c ?0 40 ms i/o port characteristics table 14. i/o port characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit i il low ?eve? in?ut cu??ent ?.?v io v i = 0v ? on-chi? ?u??-u? ?esiste? disab?ed. ? a 5v-to ?e?ant io ? a reset ?in ? a i ih high ?eve? in?ut cu??ent ?.?v io v i = v dd??? on-chi? ?u??-down ?esiste? disab?ed. ? a 5v-to ?e?ant io ? a reset ?in ? a v il low ?eve? in?ut vo?tage ?.?v io -0.? 0.8 v 5v-to ?e?ant io -0.? 0.8 v reset ?in -0.? 0.8 v v ih high ?eve? in?ut vo?tage ?.?v io ? ?.6 v 5v-to ?e?ant io ? 5.5 v reset ?in ? 5.5 v v hys schmitt t ?igge? in?ut vo ?tage hyste?esis ?.?v io 400 mv 5v-to ?e?ant io 400 mv reset ?in 400 mv
rev. 1.10 ?7 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? electrical characteristics electrical characteristics symbol parameter conditions min typ max unit i ol low ?eve? out?ut cu??ent (gpo sink cu??ent) ?.?v 4m? d?ive io? v ol = 0.4v 4 m? ?.?v 8m? d?ive io? v ol = 0.4v 8 m? 5v-to ?e?ant 8m? d?ive io? v ol =0.4v 8 m? 5v-to ?e?ant 1?m? d?ive io? v ol =0.4v 1? m? backu? domain io d? ive @ v b ? t =?.?v ? v ol = 0.4v ? pb8? pb9? pb10. 1 m? i oh high ?eve? out?ut cu??ent (gpo sou?ce cu??ent) ?.?v i/o 4m? d?ive? v oh =v dd?? -0.4v 4 m? ?.?v i/o 8m? d?ive? v oh =v dd?? -0.4v 8 m? 5v-to ?e?ant i/o 8m? d?ive? v oh = v dd?? - 0.4v 8 m? 5v-to ?e?ant i/o 1?m? d?ive? v oh = v dd?? - 0.4v 1? m? backu? domain io d?ive@v b ? t =?.?v ? v oh = v dd?? - 0.4v ? pb8? pb9? pb10. 1 m? v ol low ? eve ? out ? ut vo ? tage ?.?v 4m? d?ive io? i ol = 4m? 0.4 v ?.?v 8m? d?ive io? i ol = 8m? 0.4 v 5v-to ?e?ant 8m? d?ive io? i ol =8m? 0.4 v 5v-to ?e?ant 1?m? d?ive io? i ol =1?m? 0.4 v v oh high ?eve? out?ut vo?tage ?.?v 4m? d?ive io? i oh = 4m? v dd?? - 0.4v v ?.?v 8m? d?ive io? i oh = 8m? v dd?? - 0.4v v 5v-to ?e?ant 8 m? d?ive io? i oh =8m? v dd?? - 0.4v v 5v-to ?e?ant 1? m? d?ive io? i oh =1?m? v dd?? - 0.4v v r pu inte?na? ?u??-u? ?esisto? ?.?v i/o ?4 74 k 5v-to ?e?ant i/o ?8 89 k r pd inte?na? ?u??-down ?esisto? ?.?v i/o ?9 86 k 5v-to ?e?ant i/o ?5 107 k
rev. 1.10 ?8 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? electrical characteristics adc characteristics table 15. adc characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit v dd? o?e? ating vo?tage ?.7 ?.? ?.6 v v ?dcin ?/d conve?te? in?ut vo?tage range 0 v dd? v i ?dc cu??ent consum?tion v dd? = ?.?v 1 tbd m? i ?dc_dn powe? down cu??ent consum?tion v dd? = ?.?v 1 10 u? f ?dc ?/d conve?te? c?ock 0.7 14 mhz f s sam??ing rate 0.05 1 mhz f ?dcconv ?/d conve?te? conve? sion time 14 t ?dc r i in?ut sam??ing switch resistance 1 k c i in?ut sam??ing ca?acitance no ?in/?ad ca?acitance inc?uded 5 ?f t su sta?tu? time 1 us n ?/d conve?te? reso?ution 1? bits inl integ?a? non-?inea?ity e??o? f s = 1mhz? v dd? = ?.?v - ? 5 lsb dnl diffe ?entia? non-?inea? ity e??o? f s = 1mhz? v dd? = ?.?v 1 lsb e o offset e ??o? 10 lsb e g gain e??o? 10 lsb notes: 1. gua?anteed by design? not tested in ??oduction. 2. the figu ? e be? ow shows the equiva? ent ci? cuit of the ? /d conve?te? sam??e-and-ho? d in? ut stage whe?e c i is the sto?age ca?acito ?? r i is the ?esistance of the sam??ing switch and r s is the out? ut im? edance of the signa? sou?ce v s . no ?ma??y the sam??ing ?hase du?ation is a???oximate?y ? 1.5/f ?dc . the ca?acitance? c i ? must be cha?ged within this time f?ame and it must be ensu?ed that the vo?tage at its terminals becomes suffciently close to v s fo? accu? acy. to gua? antee this? r s may not have an a?bit?a?i?y ?a?ge va?ue. sar adc c i sample r i r s v s figure 6. adc sampling network model
rev. 1.10 ?9 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? electrical characteristics electrical characteristics the worst case occurs when the extremities of the input range (0v and vref) are sampled consecutively. in this situation a sampling error below ? lsb is ensured by using the following equation: i n i adc s r c f r ? < + ) 2 ln( 5 . 1 2 where f adc is the adc clock frequency and n is the adc resolution (n = 12 in this case). a safe margin should be considered due to the pin/pad parasitic capacitances, which are not accounted for in this simple model. if, in a system where this a/d converter is used, there are no rail-to-rail input voltage variations between consecutive sampling phases, rs may be larger than the value indicated by the equation above. operation amplifer/comparator characteristics table 16. opa/cmp characteristics t ? = ?5 c xqohvvrwkhulvhvshflhg symbol parameter conditions min typ max unit v dd? o?e? ating vo?tage ?.7 ?.? ?.6 v i op ?/cmp ty ?ica? o?e?ating cu??ent ??0 u? i op ?/cmp_dn powe? down su???y cu??ent ?ssign ?egiste?s op ?en = 0 and en_op ? op = 0 0.1 u? v ios in? ut offset vo?tage v dd? = ?.?v ? ?nof[5:0] = 100000 -15 15 mv v dd? = ?.?v ? ?fte? ca?ib?ation -1 1 mv v ios_drift in? ut offset vo?tage d?ift t ? = -40 c ~ +85c 0.04 mv/c r input in?ut resistance 10 m w gv vo ?tage gain 60 100 db u t unit-gain bandwidth r l n 1?? mhz r l n& l =100?f 1.?4 v cm common mode vo ?tage range v dd? = ?.?v v ss? v dd? C 1.? v v ov op ? out? ut vo?tage wwing v dd? = ?.?v v ss? +0.? v dd? C 0.5 v/us t rt com?a?ato? res? onse time v dd? = ?.? v; in?ut ove?d?ive = 10mv 1.6 us sr s?ew rate v dd? = ?.? v; out?ut ca?acito? ?oad c l =100?f 1 v/us note: gua?anteed by design? not tested in ??oduction. gptm characteristics table 17. gptm characteristics symbol parameter conditions min typ max unit f gptm time ? c?ock sou?ce 7? mhz t res time ? ?eso?ution time 1 1/f gptm f ext exte?na? signa? f?equency on channe? 1 ~ 4 1/? f gptm res time ? ?eso?ution 16 bits
rev. 1.10 ?0 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? electrical characteristics i 2 c characteristics table 18. i 2 c characteristics symbol parameter conditions min typ max unit f scl scl c ?ock f?equency 400 khz t scl(h) scl c ?ock high time 600 ns t scl(l) scl c ?ock ?ow time 1?00 ns t f ?ll scl and sd ? fa?? time ?00 ns t rise scl and sd ? ?ise time ?00 ns t su(st ?) st ? rt condition setu? time 600 ns t h(st ?) st ? rt condition ho?d time 600 ns t su(sd?) sd? data setu? time 100 ns t h(sd?) sd? data ho?d time 0 ns t su(sto) stop condition setu ? time 600 ns t su(sta) t h(sta) t fall t scl(l) t rise t scl(h) t h(sda) t su(sda) t su(sto) scl sda figure 7. i 2 c timing diagram
rev. 1.10 ?1 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? electrical characteristics electrical characteristics spi characteristics table 19. spi characteristics symbol parameter conditions min typ max unit f sck sck c?ock f?equency f pclk /4 mhz t sck(h) sck c?ock high time f pclk /8 ns t sck(l) sck c?ock ?ow time f pclk /8 ns spi maste? mode t v(mo) data out?ut va?id time 5 ns t h(mo) data out?ut ho?d time ? ns t su(mi) data in?ut setu? time 5 ns t h(mi) data in?ut ho?d time 5 ns spi s?ave mode t su(sel) sel enab ?e setu? time 4 t pclk ns t h(sel) sel enab ?e ho?d time ? t pclk ns t ?(so) data out?ut access time ? t pclk ns t dis(so) data out?ut disab?e time 10 ns t v(so) data out?ut va?id time ?5 ns t h(so) data out?ut ho?d time 15 ns t su(si) data in?ut setu? time 5 ns t h(si) data in?ut ho?d time 4 ns sck (cpol = 0) sck (cpol = 1) mosi miso mosi miso t sck(h) t sck(l) t sck data valid data valid data valid data valid data valid data valid data valid data valid t v(mo) cpha = 0 cpha = 1 t h(mo) t h(mi) t su(mi) t v(mo) t h(mo) t su(mi) t h(mi) data valid data valid data valid data valid figure 8. spi timing diagram C spi master mode
rev. 1.10 ?? of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? electrical characteristics sck (cpol=0) sck (cpol=1) mosi miso t sck(h) t sck(l) t sck msb/lsb out msb/lsb in t v(so) t h(so) t su(si) t h(si) sel lsb/msb out lsb/msb in t a(so) t su(sel) t dis(so) t h(sel) figure 9. spi timing diagram C spi slave mode and cpha=1
rev. 1.10 ?? of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? electrical characteristics package information 5 package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website (http://www.holtek.com.tw/english/literature/package.pdf) for the latest version of the package information. 48-pin lqfp (7mmx7mm) outline dimensions 48-pin lqfp (7mm 7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.350 0.358 b 0.272 0.280 c 0.350 0.358 d 0.272 0.280 e 0.020 f 0.008 g 0.053 0.057 h 0.063 i 0.004 j 0.018 0.030 k 0.004 0.008 07 symbol dimensions in mm min. nom. max. a 8.90 9.10 b 6.90 7.10 c 8.90 9.10 d 6.90 7.10 e 0.50 f 0.20 g 1.35 1.45 h 1.60 i 0.10 j 0.45 0.75 k 0.10 0.20 07 package information 1 may 12, 2010 symbol dimensions in inch min. nom. max. ? 0.?50 D 0.?58 b 0.?7? D 0.?80 c 0.?50 D 0.?58 d 0.?7? D 0.?80 e D 0.0?0 D f D 0.008 D g 0.05? D 0.057 h D D 0.06? i D 0.004 j 0.018 D 0.0?0 k 0.004 D 0.008 0 D 7
rev. 1.10 ?4 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? package information symbol dimensions in mm min. nom. max. ? 8.90 D 9.10 b 6.90 D 7.10 c 8.90 D 9.10 d 6.90 D 7.10 e D 0.50 D f D 0.?0 D g 1.?5 D 1.45 h D D 1.60 i 0.10 j 0.45 D 0.75 k 0.10 D 0.?0 0 D 7
rev. 1.10 ?5 of ?5 ???i? 1?? ?01? ??-bit ?rm co?tex?-m? mcu ht??f1?51/51b/5?/5? package information package information holtek semiconductor inc. (headquarters) no.?? c?eation rd. ii? science pa?k? hsinchu? taiwan te ?: 886-?-56?-1999 fax: 886-?-56? -1189 htt? ://www.ho?tek.com.tw holtek semiconductor inc. (taipei sales offce) 4f-?? no. ?-?? yuanqu st.? nankang softwa?e pa?k? tai? ei 115? taiwan te ?: 886-?-?655-7070 fax: 886-?-?655-7?7? fax: 886-?-?655-7?8? (inte?nationa? sa?es hot?ine) holtek semiconductor inc. (shenzhen sales offce) 5f ? unit ?? p?oductivity bui?ding? no.5 gaoxin m ?nd road? nanshan dist?ict? shenzhen? china 518057 te ?: 86-755-8616-9908? 86-755-8616-9?08 fax: 86-755-8616-97?? holtek semiconductor (usa), inc. (north america sales offce) 467?9 f?emont b?vd.? f?emont? c? 945?8? us? te ?: 1-510-?5?-9880 fax: 1-510-?5?-9885 htt? ://www.ho?tek.com co?y?ight ? ? 011 by holtek semiconductor inc. the info?mation a??ea? ing in this data sheet is be? ieved to be accu? ate at the time of ?ub? ication. howeve ?? ho? tek assumes no ?es?onsibi? ity a?ising f ? om the use of the s ? ecifications desc? ibed. the a??? ications mentioned he ? ein a? e used so?e? y fo? the ?u?? ose of i??ust? ation and ho? tek makes no wa?? anty o? representation that such applications will be suitable without further modifcation, nor recommends the use of its ?? oducts fo? a??? ication that may ??esent a ? isk to human ? ife due to ma?function o? othe?wise. ho?tek's ??oducts a?e not autho? ized fo? use as c?itica? com?onents in ?ife su??o?t devices o? systems. ho?tek ?ese?ves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at htt? ://www.ho?tek.com.tw .

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